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lh543601 256 36 2 bidirectional fifo features fast cycle times: 20/25/30/35 ns pin-compatible and functionally-compatible 0.7 m -technology replacement for sharp lh5420 two 256 36-bit fifo buffers full 36-bit word width selectable 36/18/9-bit word width on port b independently-synchronized (fully-asynchronous) operation of port a and port b synchronous enable-plus-clock control at both ports r/ w, enable, request, and address control inputs are sampled on the rising clock edge synchronous request/acknowledge handshake capability; use is optional device comes up into a known default state at reset; programming is allowed, but is not required asynchronous output enables five status flags per port: full, almost-full, half-full, almost-empty, and empty almost-full flag and almost-empty flag are programmable mailbox registers with synchronized flags data-bypass function data-retransmit function automatic byte parity checking 8 ma-i ol high-drive three-state outputs with built-in series resistor ttl/cmos-compatible i/o space-saving pqfp and tqfp packages pqfp to pga package conversion 1 functional description the lh543601 contains two fifo buffers, fifo #1 and fifo #2. these operate in parallel, but in opposite directions, for bidirectional data buffering. fifo #1 and fifo #2 each are organized as 256 by 36 bits. the lh543601 is ideal either for wide unidirectional applica- tions or for bidirectional data applications; component count and board area are reduced. the lh543601 has two 36-bit ports, port a and port b. each port has its own port-synchronous clock, but the two ports may operate asynchronously relative to each other. data flow is initiated at a port by the rising edge of the appropriate clock; it is gated by the corresponding edge- sampled enable, request, and read/write control signals. at the maximum operating frequency, the clock duty cycle may vary from 40% to 60%. at lower frequencies, the clock waveform may be quite asymmetric, as long as the minimum pulse-width conditions for clock-high and clock-low remain satisfied; the lh543601 is a fully-static part. conceptually, the port clocks ck a and ck b are free- running, periodic clock waveforms, used to control other signals which are edge-sensitive. however, there actually is not any absolute requirement that these clock wave- forms must be periodic. an asynchronous mode of operation is possible, in one or both directions, inde- pendently, if the appropriate enable and request inputs are continuously asserted, and enough aperiodic clock pulses of suitable duration are generated by external logic to cause all necessary actions to occur. a synchronous request/acknowledge handshake facility is provided at each port for fifo data access. this request/ acknowledge handshake resolves fifo full and empty boundary conditions, when the two ports are op- erated asynchronously relative to each other. fifo status flags monitor the extent to which each fifo buffer has been filled. full, almost-full, half-full, almost-empty, and empty flags are included for each fifo. the almost-full and almost-empty flags are pro- grammable over the entire fifo depth, but are automat- ically initialized to eight locations from the respective fifo boundaries at reset. a data block of 256 or fewer words may be retransmitted any desired number of times. note: 1. for pqfp-to-pga conversion for thru-hole board designs, sharp recommends itt pomona electronics smt/pga generic converter model #5853. ? this converter maps the lh543601 132-pin pqfp to a generic 13 13, 132-pin pga (100-mil pitch). for more information, contact sharp or itt pomona electronics at 1500 east ninth street, pomona, ca 91766, (909) 469-2900. 1
functional description (contd) two mailbox registers provide a separate path for passing control words or status words between ports. each mailbox has a new-mail-alert flag, which is syn- chronized to the reading ports clock. this mailbox func- tion facil itates the syn chronization of data transfers between asynchronous systems. data-bypass mode allows port a to directly transfer data to or from port b at reset. in this mode, the device acts as a registered transceiver under the control of port a. for instance, a master processor on port a can use the data bypass feature to send or receive initializa- tion or configuration information directly, to or from a peripheral device on port b, during system startup. a word-width-select option is provided on port b for 36-bit, 18-bit, or 9-bit data access. this feature al lows word-width matching between port a and port b, with no additional logic needed. it also ensures maximum ut iliza- tion of bus bandwidths. a byte parity check flag at each port monitors data integrity. control-register bit 0 (zero) selects the parity mode, odd or even. this bit is initialized for odd data parity at reset; but it may be reprogrammed for even parity, or back again to odd parity, as desired. 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 v cco d 10a d 9a d 8a v sso d 7a d 6a d 5a d 4a d 3a d 2a d 1a d 0a rs rt 1 d 1b d 2b d 3b d 4b d 5b d 6b d 7b d 8b d 9b d 10b d 11b v cco v sso v sso v cco v sso v cco 49 50 d 0b 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 v cco d 24a d 25a d 26a v sso d 27a d 28a d 29a d 30a d 31a d 32a d 33a d 34a d 35a rt 2 d 35b d 34b d 33b d 32b d 31b d 30b d 29b d 28b d 27b d 26b d 25b v cco v sso v ss v sso v cco v sso v cco 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 pin 1 pin 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 d 12a d 13a d 14a v sso d 15a d 16a d 17a hf 1 af 1 ff 1 oe a a 2a a 1a a 0a r/w a en a v ss ack a ef 2 mbf 2 d 18a d 19a d 20a d 21a d 22a v cc ck a req a ae 2 v sso d 23 a d 11a d 12b d 13b d 14b v sso d 15b d 16b d 17b ae 1 ef 1 req b en b r/w b ck b ws 0 ws 1 v cc ff 2 af 2 pf b d 18b d 19b d 20b d 21b d 22b v ss a 0b hf 2 v sso d 23 b mbf 1 ack b oe b d 24 b pf a 543601-30 top view chamfered edge figure 1. pin connecti ons for 132-pin pqfp package (top view) pin connections lh543601 256 36 2 bidirectional fifo 2
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 nc d 24a d 25a d 27a d 28a d 30a d 31a d 33a nc d 34b d 33b d 31b d 30b d 28b d 27b 32 33 rt 2 128 127 nc v cco d 10a d 9a v sso d 7a d 6a v cco d 4a d 3a v sso d 1a rs nc d 0b d 2b v sso d 3b d 5b v cco d 6b d 8b v sso d 9b d 5a d 2a d 1b d 4b d 7b d 10b 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 d 23a d 22a d 21a v sso d 19a d 18a ae 2 ef 2 ack a req a en a r/w a ck a a 0a oe a v cc ff 1 hf 1 pf a d 17a d 15a v sso d 14a v ss nc af 1 d 13a nc nc d 24b d 23b v sso d 22b d 20b pf b oe b ws 1 nc a 0b r/w b en b req b ack b ef 1 mbf 1 d 16b v sso v ss d 17b d 15b hf 2 ck b d 14b top view mbf 2 543601-38 34 35 36 v cco nc d 11b v cco nc 75 74 73 111 110 d 12a d 11a nc 109 53 54 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 d 13b d 12b nc v cco d 26a v sso d 29a v cco d 32a v sso d 34a d 35a v sso d 32b v cco d 29b v sso d 26b d 25b d 21b d 19b d 18b af 2 ff 2 v cc ws 0 ae 1 d 8a rt 1 d 0a d 20a a 1a a 2a d 16a d 35b v ss 144-pin tqfp figure 2. pin connections for 144- pin tqfp package (top view) 256 36 2 bidirectional fifo lh543601 3
pin list signal name pqfp pin no. tqfp pin no. a 0a 1 126 a 1a 2 125 a 2a 3 124 oe a 4 123 ff 1 6 121 af 1 7 120 hf 1 8 119 pf a 9 118 d 17a 10 117 d 16a 11 116 d 15a 12 115 d 14a 14 113 d 13a 15 112 d 12a 16 111 d 11a 17 110 d 10a 19 106 d 9a 20 105 d 8a 21 104 d 7a 23 102 d 6a 24 101 d 5a 25 100 d 4a 27 98 d 3a 28 97 d 2a 29 96 d 1a 31 94 d 0a 32 93 rs 33 92 rt 1 34 91 d 0b 35 89 d 1b 36 88 d 2b 37 87 d 3b 39 85 d 4b 40 84 d 5b 41 83 d 6b 43 81 d 7b 44 80 d 8b 45 79 d 9b 47 77 d 10b 48 76 d 11b 49 75 d 12b 51 71 d 13b 52 70 d 14b 53 69 d 15b 54 68 signal name pqfp pin no. tqfp pin no. d 16b 56 66 d 17b 57 65 mbf 1 58 64 ae 1 59 63 ef 1 60 62 ack b 61 61 req b 63 59 en b 64 58 r/ w b 65 57 ck b 66 56 a 0b 67 55 ws 0 68 53 ws 1 69 52 oe b 70 51 ff 2 72 49 af 2 73 48 hf 2 74 47 pf b 75 46 d 18b 76 45 d 19b 77 44 d 20b 78 43 d 21b 80 41 d 22b 81 40 d 23b 82 39 d 24b 83 38 d 25b 85 34 d 26b 86 33 d 27b 87 32 d 28b 89 30 d 29b 90 29 d 30b 91 28 d 31b 93 26 d 32b 94 25 d 33b 95 24 d 34b 97 22 d 35b 98 21 rt 2 100 18 d 35a 101 17 d 34a 102 16 d 33a 103 15 d 32a 105 13 d 31a 106 12 d 30a 107 11 d 29a 109 9 signal name pqfp pin no. tqfp pin no. d 28a 110 8 d 27a 111 7 d 26a 113 5 d 25a 114 4 d 24a 115 3 d 23a 117 143 d 22a 118 142 d 21a 119 141 d 20a 120 140 d 19a 122 138 d 18a 123 137 mbf 2 124 136 ae 2 125 135 ef 2 126 134 ack a 127 133 req a 129 131 en a 130 130 r/ w a 131 129 ck a 132 128 v cc 5 122 v sso 13 114 nc 109 nc 108 v cco 18 107 v sso 22 103 v cco 26 99 v sso 30 95 nc 90 v sso 38 86 v cco 42 82 v sso 46 78 v cco 50 74 nc 73 nc 72 v sso 55 67 v ss 62 60 nc 54 v cc 71 50 v sso 79 42 nc 37 nc 36 v cco 84 35 v sso 88 31 v cco 92 27 note: pins comments v cc supply internal logic. connected to each other. v cco supply output drivers only. connected to each other. pins comments v ss supply internal logic. connected to each other. v sso supply output drivers on ly. co nnected to each other. lh543601 256 36 2 bidirectional fifo 4
reset logic port a i/o rs port a synch- ronous control logic read pointer write pointer fixed and programmable status flags fifo #1 memory array 256 x 36 mailbox register #2 read pointer write pointer fifo #2 memory array 256 x 36 port b i/o ff 1 hf 1 af 1 ef 2 ae 2 ef 1 ae 1 ff 2 hf 2 af 2 ws 0 , ws 1 d 0a - d 35a oe a ack a req a en a r/w a ck a d 0b - d 35b oe b rt 1 ack b req b en b r/w b ck b command port and register a 0b parity checking resource registers parity checking a 0a a 1a a 2a rt 2 command port and register mailbox register #1 bypass mbf 1 mbf 2 port b synch- ronous control logic fixed and programmable status flags 543601-6 pf a pf b figure 3b. detailed lh543601 block diagram fifo 1 port a i/o fifo 2 port b i/o write read write read port a control port b control 543601-36 figure 3a. simplified lh543601 block diagram 256 36 2 bidirectional fifo lh543601 5
pin descriptions pin pin type 1 description general v cc , v ss v power, ground rs i reset port a ck a i port a free-running clock r/ w a i port a edge-sampled read/write control en a i port a edge-sampled enable a 0a , a 1a , a 2a i port a edge -sampled address pins oe a i port a level-sensitive output en able req a i port a request/enable rt 2 i fifo #2 retransmit d 0a C d 35a i/o/z port a bidirectional data bus ff 1 o fifo #1 full flag (write boundary) af 1 o fifo #1 programmable almost-full flag (write bo undary) hf 1 o fifo #1 half-full flag ae 2 o fifo #2 programmable almost-empty flag (read boundary) ef 2 o fifo #2 empty flag (read boundary) mbf 2 o new-mail-alert flag for mailbox #2 pf a o port a parity flag ack a o port a acknowledge port b ck b i port b free-running clock r/ w b i port b edge-sampled read/write control en b i port b edge-sampled enable a 0b i port b edge -sampled address pin oe b i port b level-sensitive output enable ws 0 , ws 1 i port b word-width select req b i port b request/ enable rt 1 i fifo #1 retransmit d 0b C d 35b i/o/z port b bidirectional data bus ff 2 o fifo #2 full flag (write boundary) af 2 o fifo #2 programmable almost-full flag (write boundary) hf 2 o fifo #2 half-full flag ae 1 o fifo #1 programmable almost-empty flag (read boundary) ef 1 o fifo #1 empty flag (read boundary) mbf 1 o new-mail-alert flag for mailbox #1 pf b o port b parity flag ack b o port b acknowledge note: 1. i = input, o = output, z = high-imp edance, v = power voltage level lh543601 256 36 2 bidirectional fifo 6
absolute maximum ratings 1 parameter r ating suppl y vol tage to v ss potential C0.5 v to 7 v signal pin voltage to v ss potential 3 C0.5 v to v cc + 0.5 v dc output current 2 40 ma storage temperature range C6 5 o c to 150 o c power dissipation (package limit) 2 watts (quad flat pack) notes: 1. stresses greater than those listed under a bsol ute maximum ratings may cause permanent damage to the device. this is a stress rating for transient conditions only. functional operation of the device at these or any other c onditions outside those indicated in the operating range of this specification is not implied. ex posure to absolute maxi mum rating conditions for extended p eriods may affect reliability. 2. outputs should not be shorted for more than 30 seconds. no more than one output should be shorted at any time. 3. negative undershoot of 1.5 v in amplitude is permit ted for up to 10 ns, once per cycle. operating range symbol parameter min max unit t a temperature, ambient 070 o c v cc supply voltage 4.5 5.5 v v ss supply voltage 00v v il logic low input voltage 1 C0.5 0.8 v v ih logic high input voltage 2.2 vcc + 0.5 v note: 1. negative undershoot of 1.5 v in amplitude is permitted for up to 10 ns, once per cycle. dc electrical characteristics (over operat ing range) symbol parameter test cond itions min typ max unit i li input leakage current v cc = 5.5 v, v in = 0 v to v cc C10 10 m a i lo i/o l eakage current oe 3 v ih , 0 v v out v cc C10 10 m a v ol logic low output voltage i ol = 8.0 ma 0.4 v v oh logic high output voltage i oh = C8.0 ma 2.4 v i cc average supply current 1, 2 measured at f cc = max 180 280 ma i cc2 average standby supply current 1, 3 all inputs = v ihmin (clocks idle) 13 25 ma i cc3 power-down supply current 1 all inputs = v cc C 0.2 v (clocks idle) 0.002 0.4 ma i cc4 power-down supply current 1, 3 all inputs = v cc C 0.2 v (clocks at fcc = max) 610ma notes: 1. i cc , i cc 2 , i cc3 , and i cc 4 are depen dent upon actual output loadi ng, and i cc and i cc 4 are also dep endent on cycle rates. spe cified val ues are with outputs open (for i cc : c l = 0 pf); and, for i cc and i cc 4 , operating at minimum cycle ti mes. 2. i cc (max.) using worst case conditions and data pattern. i cc (typ.) using v cc = 5 v and and average data pattern. 3. i cc 2 (typ.) and i cc4 (typ.) using v cc = 5 v and t a = 25 c. 543601-39 to associated input buffer, if any (see note) from port internal data bus (or control gate) d na/b (or flag) 15 w note: output-only pins have no associated input buffer. figure 4. structure of series resistor input/output interface 256 36 2 bidirectional fifo lh543601 7
ac test conditions parameter rating input pulse levels v ss to 3 v input rise and fall times (10% to 90%) 5 ns output reference levels 1.5 v input timing reference levels 1.5 v output load, timing tests figure 5 capacitance 1,2 parameter rating c in (input capacitance) 8 pf c out (output capacitance) 8 pf notes: 1. sample tested only. 2. capacitances are ma ximum values at 25 o c, measured at 1.0mhz, with v in = 0 v. device under test +5 v 30 pf 470 w 240 w includes jig and scope capacitances * * 543601-7 figure 5. output load circuit lh543601 256 36 2 bidirectional fifo 8
ac electrical characteristics 1 (v cc = 5 v 10%, t a = 0 c to 70 c) symbol decription C20 C25 C30 C35 units mi n max min max min max mi n max f cc clock cycle frequency 50 40 33 28.5 mhz t cc clock cycle time 20 25 30 35 ns t ch clock high time 8 10 12 15 ns t cl clock low time 8 10 12 15 ns t ds data setup time 10 12 13 15 ns t dh data hold time 0000ns t es enable setup time 10.4 13 15 15 ns t eh enable hold time 0000ns t rws read/write setup time 10.4 13 15 18 ns t rwh read/write hold time 0000ns t rqs request setup time 12 15 18 21 ns t rqh request hold time 0000ns t as address setup time 6 12151821ns t ah address hold time 6 0000ns t a data output access time 12.8 16 20 25 ns t ack acknowledge access time 12 15 20 25 ns t oh output hold time 2.0 2.0 2.0 2.0 ns t zx output enable time, oe low to d 0 C d 35 low-z 2 1.5 2.0 3.0 3.0 ns t xz output disable time, oe high to d 0 C d 35 high-z 2 9 121520ns t ef clock to ef flag valid (empty flag) 17.6 22 25 30 ns t ff clock to ff flag valid (full flag) 17.6 22 25 30 ns t hf clock to hf flag valid (half-full) 17.6 22 25 30 ns t ae clock to ae flag valid (almost- empty) 16202530ns t af clock to af flag valid (almost-full) 16 20 25 30 ns t mbf clock to mbf flag valid (mailbox flag) 12152025ns t pf data to parity flag valid 13.6 17 20 25 ns t rs reset/retransmit pulse width 7 32/20 40/25 52/30 65/35 ns t rss reset/retransmit setup time 3 16202530ns t rsh reset/retransmit hold time 3 8 101520ns t rf reset low to flag valid 28 35 40 45 ns t frl first read latency 4 20253035ns t fwl first write latency 5 20253035ns t bs bypass data setup 12 15 18 21 ns t bh bypass data hold 3555ns t ba bypass data access 18 20 25 30 ns notes: 1. timing measurements performed at ac test c ondi tion levels. 2. values are guaranteed by desi gn; not currently production tested. 3. t rss and/or t rsh need not be met unless a rising edge of ck a occurs while en a is being asserted, or else a rising e dge of ck b occurs while en b is being asserted. 4. t frl is the minimum fi rst-w rite-to-first-read delay, following an empty condition, which is required to assure valid read data. 5. t fwl is the minimum first-read-to-first-write delay, following a full condtion, which is requi red to as sure successful writing of data. 256 36 2 bidirectional fifo lh543601 9
operational description reset the device is reset whenever the asynchronous reset ( rs) input is taken low, and at least one rising e dge and one falling edge of both ck a and ck b occur while rs is low. a reset operation is required after power-up, before the first write operat ion may occur. the lh543601 is fully ready for operation after being reset. no device program- ming is required if the default states described below are acceptable. a reset operation initial izes the read-address and write-address pointers for fifo #1 and fifo #2 to t hose fifos first physical memory locations. if the respective outputs are enabled, the initial contents of these first locations appear at the outputs. fifo and mailbox status flags are updated to indicate an empty condition. in addition, the programmable-status-flag offset values are initialized to eight. thus, the ae 1 / ae 2 flags get asserted within eight locations of an empty condition, and the af 1 / af 2 flags likewise get asserted within eight locations of a full condition, for fifo #1/fifo #2 respectively. bypass operation during reset (whenever rs is low) the device acts as a registered transceiver, bypassing the internal fifo memories. port a acts as the master port. a write or read operation on port a during reset transfers data directly to or from port b. port b is considered to be the slave, and cannot perform write or read operations indepen dently on its own during reset. the direction of the bypass data transmission is deter- mined by th r/ w a control input, which does not get overridden by the rs input. here, a write operation means passing data from port a to port b, and a read operation means passing data from port b to port a. the bypass c apability may be used to pass initializa- tion or configuration data directly between a master proc- essor and a peripheral device during reset. address modes address pins select the device resource to be accessed by each port. port a has three resource-r egis- ter-select inputs, a 0a , a 1a , and a 2a , which select between fifo access, mailbox-register acc ess, control-register access (write only), and programmable flag-offset-value- register access. port b has a single address input, a 0b , to select between fifo access or mailbox-regi ster ac- cess. the status of the resource-r egister-select inputs is sampled at the rising edge of an enabled clock (ck a or ck b ). resource-register select-input addr ess def initions are summarized in table 1. fifo write port a writes to fifo #1, and port b writes to fifo #2. a write operation is initiated on the rising edge of a clock (ck a or ck b ) whenever: the app ropriate ena ble (en a or en b ) is held high; the appropriate request (req a or req b ) is held high; the appropriate read/write control (r/ w a or r/ w b ) is held low; the fifo address is selected for the address inputs (a 2a C a 0a or a 0b ); and the prescribed setup times and hold times are observed for all of these signals. setup times and hold times must also be observed on the data-bus pins (d 0a C d 35a or d 0b C d 35b ). normally, the appropriate output enable signal ( oe a or oe b ) is high, to disable the outputs at that port, so that the data word present on the bus from external sources gets stored. however, a loopback m ode of operation also is possible, in which the data word supplied by the outputs of one internal fifo is turned around at the port and read back into the other fifo. in this mode, the outputs at the port are not disabled. to remain within specification for all timing parameters, the clock cycle frequency must be reduced sligh tly below the value which otherwise wo uld be permissible for that speed grade of lh543 601. when a fifo full condition is reached, write operat ions are locked out. following the first read operation from a full fifo, another memory location is fr eed up, and the corresponding full flag is deasserted ( ff = high). the first write operation should begin no earlier than a first write latency (t fwl ) after the first read operation from a full fifo, to ensure that correct read data are retrieved. fifo read port a reads from fifo #2, and port b reads from fifo #1. a read operation is initiated on the rising edge of a clock (ck a or ck b ) whenever: the appropriate enable (en a or en b ) is held high; the appropriate request (req a or req b ) is held high; the appropriate read/write control (r/ w a or r/ w b ) is held high; the fifo address is selected for the address inputs (a 2a C a 0a or a 0b ); and the prescribed setup times and hold times are observed for all of these signals. read data table 1. resource-register addresses a 2a a 1a a 0a resource port a hhh fifo hh l mailbox hlh af 2 , ae 2 , af 1 , ae 1 flag offsets register (36-bit mode) hl l control register (par ity mode) lhh ae 1 flag offset register lhl af 1 flag offset register llh ae 2 flag offset register lll af 2 flag offset register a 0b resource port b h fifo l mailbox lh543601 256 36 2 bidirectional fifo 10
becomes valid on the data-bus pins (d 0a C d 35a or d 0b C d 35b ) by a time t a after the rising clock (ck a or ck b ) edge, provided that the data outputs are enabled. oe a and oe b are assertive-low, asynchronous, out- put enable cont rol input signals. their effect is only to enable or disable the output drivers of the respective port. disabling the outputs does not disable a read operation; data transmitted to the corresponding output register will remain available later, when the outputs again are en- abled, unless it subsequently is overwritten. when an empty condition is reached, read operations are locked out until a valid write operat ion(s) has loaded additional data into the fifo. following the first write to an empty fifo, the corresponding empty flag ( ef) will be deasserted (high). the first read operation should begin no earlier than a first read latency (t frl ) after the first write to an empty fifo, to ensure that correct read data words are retrieved. dedicated fifo status flags six dedicated fifo status flags are included for full ( ff 1 and ff 2 ), half-full ( hf 1 and hf 2 ), and empty ( ef 1 and ef 2 ). ff 1 , hf 1 , and ef 1 indicate the status of fifo #1; and ff 2 , hf 2 , and ef 2 indicate the status of fifo #2. a full flag is asserted following the first subsequent rising clock edge for a write operation which fills the fifo. a full flag is deasserted following the first subsequent falling clock edge for a read operation to a full fifo. a half-full flag is updated following the f irst subsequent rising clock edge of a read or write operation to a fifo which changes its half-fu ll status. an empty flag is asserted following the first subsequent rising clock edge for a read operation which empties the fifo. an empty flag is deasserted f ollowing the falling c lock edge for a write operation to an empty fifo. programmable status flags four programmable fifo status flags are provided, two for almost-full ( af 1 and af 2 ), and two for almost- empty ( ae 1 and ae 2 ). thus, each port has two program- mable flags to monitor the status of the two internal fifo buffer memories. the offset values for these flags are initialized to eight locations from the res pective fifo boundaries during reset, but can be reprogrammed over the entire fifo depth. an almost-full flag is asserted following the first sub- sequent rising clock edge after a write operation which has part ially filled the fifo up to the almost-full offset point. an almost-full flag is dea sserted f ollowing the f irst subsequent falling clock edge after a read operation which has partially emptied the fifo down past the almost-full offset point. an almost-empty flag is as- serted following the first subsequent rising clock edge after a read operation which has partially emptied the fifo down to the almost-empty offset point. an almost- empty flag is deasserted following the first subsequent falling clock edge after a write operation which has par- tially filled the fifo up past the almost-empty offset point. flag offsets may be written or read through the port a data bus. all four programmable fifo status flag offsets can be set simultaneously through a single 36-bit status word; or, each programmable flag offset can be set individually, through one of four eight-bit status words. table 3 illustrates the data format for flag-programming words . also, table 4 defines the meaning of each of the five flags, both the dedicated flags and the programmable flags, for the lh543601. warning: control inputs which may affect the compu- tation of flag values at a port generally should not change while the clock for that port is high, since some updating of flag values takes place on the falling edge of the clock. mailbox operation two mailbox registers are provided for passing system hardware or software control/status words between ports. each port can read its own mailbox and write to the other ports mailbox. mailbox ac cess is performed on the rising edge of the controlling fifos clock, with the m ailbox address selected and the enable (en a or en b ) high. that is, writing to mailbox register #1, or reading from mailbox register #2, is synchronized to ck a ; and writing to mailbox register #2, or reading from mailbox register #1, is synchronized to ck b . the r/ w a/b and oe a/b pins control the direction and availability of mailbox-register accesses. each mailbox register has its own new-m ail-alert flag ( mbf 1 and mbf 2 ), which is synchronized to the reading ports clock. these new-mail-alert flags are status indicators only, and cannot inhibit mailbox-register read or write operations. request acknowledge handshake a synchronous request-acknowledge handshake fea- ture is provided for each port, to perform boundary syn- chronization between asynchronously-operated ports. the use of this feature is optional. when it is used, the request input (req a/b ) is sampled at a rising clock edge. with req a/b high, r/ w a/b determines whether a fifo read operation or a fifo write operation is being re- quested. the acknowledge output (ack a/b ) is updated during the following clock cycle(s). ack a/b meets the setup and hold time requirements of the enable input (en a or en b ). therefore, ack a/b may be tied back to the enable input to direc tly gate fifo accesses, at a slight decrease in maximum operating frequency. the assertion of ack a/b signifies that req a/b was asserted. however, ack a/b does not depend logically on en a/b ; and thus the assertion of ack a/b does not prove that a fifo write access or a fifo read access act ually took place. while req a/b and en a/b are being held high, ack a/b may be considered as a synchronous, predictive boundary flag. that is, ack a/b acts as a syn- operational description (contd) 256 36 2 bidirectional fifo lh543601 11
chronized predictor of the almost- full flag af for write operations, or as a synchr onized predictor of the almost- empty flag ae for read operations. outside the almost-full region and the almost-empty region, ack a/b remains cont inuously high whenever req a/b is held continuously high. within the almost-f ull region or the almost-empty region, ack a/b occurs only on every third cycle, to prevent an overrun of the fifos actual full or empty boundaries and to ensure that the t fwl (first write latency) and t frl (first read latency) specifica- tions are satisfied before ack a/b is received. the almost-full r egion is defined as that region, where the almost-full flag is being asserted; and the almost- empty region as that region, where the almost-empty flag is being asserted. thus, the extent of these almost regions depends on how the system has programmed the offset values for the almost-full flags and the almost- empty flags. if the system has not programmed them, then these offset values remain at their default values, eight in each case. if a write attempt is unsuccessful because the corre- sponding fifo is full, or if a read attempt is unsuccessful because the corresponding fifo is empty, ack a/b is not asserted in response to req a/b . if the req/ack handshake is not used, then the req a/b input may be used as a second enable input, at a possible minor loss in maximum operating speed. in this case, the ack a/b output may be ignored. warning: whether or not the req/ack handshake is being used, the req a/b input for a port must be asserted for that port to function at all C for fifo, mailbox, or data-bypass operation. data retransmit a retransmit operation resets the read-address pointer of the corresponding fifo (#1 or #2) back to the first fifo physical memory location, so that data may be reread. the write pointer is not affected. the status flags are updated; and a block of up to 256 data words, which previously had been written into and read from a fifo, can be retrieved. the block to be retransmitted is bounded by the first fifo memory location, and the fifo memory location addressed by the write pointer. fifo #1 retransmit is initiated by strobing the rt 1 pin low. fifo #2 retransmit is initiated by strobing the rt 2 pin low. read and write operations to a fifo should be stopped while the corresponding retrans- mit signal is being asserted. parity c hecking the parity check flags, pf a and pf b , are asserted (low) whenever there is a parity error in the data word present on the port a data bus or the port b data bus respectively. the inputs to the parity-evaluation logic come directly (via isolation transistors) from the data-bus bonding pads , in each case. thus, pf a and pf b provide parity-error indications for whatever 36-bit words are present at port a and port b respectively, regardless of whether those words originated within the lh543601 or in the external system. the four bytes of a 36-bit data word are grouped as d 0 C d 8 , d 9 C d 17 , d 18 C d 26 , and d 27 C d 35 . the parity of each nine-bit byte is individually checked, and the four single-bit parity indications are logically inclusive-ored and inverted, to produce the parity-flag output. parity checking is initial- ized for odd parity at reset, but can be reprogrammed for even parity or for odd parity during operation. control-reg- ister bit 00 (zero) selects the p arity mode, odd or even. (see table 3.) all nine bits of each byte are treated alike by the parity logic. the byte parity over the nine bits is compared with the parity mode bit in the control register, to generate a byte-parity-error indication. then, the four byte-parity- error signals are nored together, to compute the asser- tive-low parity-flag value. word-width selection on port b the word width of data access on port b is selected by the ws 0 and ws 1 control inputs. ws 0 and ws 1 both are tied high for 36-bit access; they both are tied low for single-byte access. for double-byte access, ws 0 is tied high and ws 1 is tied low. (see table 2.) in the single-byte-access or double-byte-access modes, fifo write operations on port b essentially pack the data to form 36-bit words, as viewed from port a. similarly, single- byte or double-byte fifo read operations on port b essen- tially unpack 36-bit words through a series of shift operations. fifo status flags are updated following the last access which forms a complete 36-bit transfer. since the values for each status flag are computed by logic directly associated with one of the two fifo-memory arrays, and not by logic associated with port b, the flag values reflect the array fullness situation in terms of com- plete 36-bit words , and not in terms of bytes or double bytes. however, there is no s uch restriction for switching from writing to reading, or from reading to writing, at port b. as long as t rws , t ds , and t a are satisfied, r/ w b may change state after any single-byte or double-byte access, and not only after a full 36-bit-word access. also, the wor d-width-matching feature continues to operate properly in loopback mode. note that the programmable word-width-matching fea- ture is only supported for fifo accesses. mailbox and data bypass operations do not support word-width matching between port a and port b. tables 2, 3, and 4, and figures 6a, 6b, 7a, and 7b summarize word-width selection for port b. table 2. port b word-width selection ws 1 ws 0 port b data width h h 36-bit h l (reserved) l h 18-bit l l 9-bit operational description (contd) lh543601 256 36 2 bidirectional fifo 12
table 3. resource-register programming resource- register address resource-register contents a 2a a 1a a 0a normal fifo operation d 35 a d 0a hhhx... ...x mailbox d 35 a d 0a hh lx... ...x af 2 , ae 2 , af 1 , ae 1 flag offsets register (36-bit mode) d 35 a d 34a . . . d 27a d 26 a d 25a . . . d 18 a d 17 a d 16 a . . . d 9a d 8a d 7a . . . d 0a hlhx af 2 offset 1 x ae 2 offset 1 x af 1 offset 1 x ae 1 offset 1 control register: (write-only) parity even/odd d 35 a d 1a d0a h l l x... ...x parity mode 2 8-bit ae 1 flag offset register d 35 a d 8a d 7a . . . d 0a lhhx... ...x ae 1 offset 1 8-bit af 1 flag off set register d 35 a d 8a d 7a . . . d 0a lhlx... ...x af 1 offset 1 8-bit ae 2 flag off set register d 35 a d 8a d 7a . . . d 0a llhx... ...x ae 2 offset 1 8-bit af 2 flag off set register d 35 a d 8a d 7a . . . d 0a l l l x... ...x af 2 offset 1 notes: 1. all four programmable-flag-offset values are in itialized to ei ght (8) during a reset operation. 2. odd parity = high; even parity = low. the parity mode is initialized to odd during a reset operation. 256 36 2 bidirectional fifo lh543601 13
table 4. flag definition table 1 flag valid read cycles remaining valid write cycles remaining flag = low flag = high flag = low flag = high min max min max min max min max ff 256 256 0 255 0 0 1 256 af 256-p 256 0 255-p 0 p p + 1 256 hf 129 256 0 128 0 127 128 256 ae 0 q q + 1 256 256-q 256 0 255-q ef 0 0 1 256 256 256 0 255 notes: 1. q = program mable-a lmost-empty offset value. (d efault value: q = 8.) 2. p = program mable-almost-full offset value. (d efault val ue: p = 8.) lh543601 256 36 2 bidirectional fifo 14
18-bit data streams 36-bit data stream 18 18 18 18 bits 18-35 (2nd halfword) bits 18-35 (2nd halfword) bits 0-17 (1st halfword) bits 0-17 (1st halfword) 2nd halfword, then 1st halfword 1st halfword, then 2nd halfword d 35a d 18a d 17a d 0a d 35b d 18b d 17b d 0b port a port b 543601-32 figure 6a. 36-to-18 funneling through fifo #1 9-bit data streams 36-bit data stream 9 9 9 9 bits 27-35 (4th byte) 4th byte, then 1st byte, then 2nd byte, then 3rd byte d 35a d 27a d 26a d 18a d 35b d 27b d 26b d 18b port a port b 9 9 9 9 d 17a d 9a d 8a d 0a d 17b d 9b d 8b d 0b bits 18-26 (3rd byte) bits 9-17 (2nd byte) bits 0-8 (1st byte) 3rd byte, then 4th byte, then 1st byte, then 2nd byte 2nd byte, then 3rd byte, then 4th byte, then 1st byte 1st byte, then 2nd byte, then 3rd byte, then 4th byte 543601-34 figure 6b. 36-to-9 funneling th rough fifo #1 port b word-width selection notes: 1. the heavy black borders on register segments indic ate the main data path, su itable for most appli cations. alternate paths feature a different o rdering of bytes within a word, at p ort b. 2. the funneling process does not change the ordering of bits within a byte. halfwords (figure 6a) or bytes (figure 6b) are trans- ferred in parallel form from port a to port b. 3. the word-width setting may be changed during system operation; however, two clock intervals should be allowed for these si gnals to settle, before again attempting to read d 0b C d 35b , and three dummy words should be passed through initially. also, incom- plete data words may occur, when the word width is changed from shorter to lo nger at an inap propriate point in the data block passing through the fifo. 256 36 2 bidirectional fifo lh543601 15
18-bit data stream 36-bit data stream 18 18 18 18 bits 18-35 (2nd halfword) bits 0-17 (1st halfword) 1st halfword, then 2nd halfword d 35a d 18a d 17a d 0a d 35b d 18b d 17b d 0b port a port b 543601-33 figure 7a. 18-to-36 defunneling through fifo #2 9-bit data stream 36-bit data stream 9 9 9 9 bits 27-35 (4th byte) d 35a d 27a d 26a d 18a d 35b d 27b d 26b d 18b port a port b 9 9 9 9 d 17a d 9a d 8a d 0a d 17b d 9b d 8b d 0b bits 18-26 (3rd byte) bits 9-17 (2nd byte) bits 0-8 (1st byte) 1st byte, then 2nd byte, then 3rd byte, then 4th byte 543601-35 figure 7b. 9-to-36 defunneling through fifo #2 port b word-width selection notes: 1. the heavy black borders on register segments indicate the only data paths used. the other byte segments of port b do not par- ticipate in the data path during defunneling. 2. the defunneling process does not change the ordering of bits within a byte. halfw ords (figure 7a) or bytes (figure 7b) are transferred in parallel form from port b to port a. 3. the word-width setting may be c hanged during system o peration; however, two clock intervals s hould be allowed for these signals to settle, before again attempting to send data, and three dummy words should be passed through initially. also, incom- plete data words may occur, when the word width is changed from shorter to longer at an i nappropriate point in the data block passing through the fifo. lh543601 256 36 2 bidirectional fifo 16
timing diagrams rs a ck en hf, af, ff, mbf a ef, ae eh t es t eh t es t rs t eh t es t eh t es t ck b en b rss t rsh t rss t rss t rsh t rss t rf t rf t notes: 1. rs overrides all other input signals, except for r/w a , en a , and req a . it operates asynchronously. rs operates whether or not en a and/or en b are asserted. however, at least one rising edge and one falling edge of both ck a and ck b must occur while rs is being asserted (is low), with timing as defined by t rss and t rsh . 2. otherwise, t rss , t rsh need not be met unless the rising edge of ck a and/or ck b occurs while that clock is enabled. 3. the parity-check even/odd selection (control register bit 00) is initialized to odd byte parity at reset (high). 4. the ae and af flag offsets are initialized to eight locations from the boundary at reset. 543601-26 req a t rqs t rqh req b t rqs t rqh t rqs t rqh t rqs t rqh figure 8. reset timing 256 36 2 bidirectional fifo lh543601 17
timing diagrams (contd) rs a ck r/w a rwh t rws t en oe b rss t rsh t eh t es t eh t es t bypass in bypass data out bh t bs t a t zx t ba t oh t oe a bypass out bypass in ba t oh t xz t bs t bh t a previous data notes: 1. t rss , t rsh need not be met unless the rising edge of ck a or ck b occurs while that clock is enabled. 2. port a is considered the master port for bypass operation. thus, ck a , r/w a , en a , and req a control the transmission of data between ports at reset. d 0b - d 35b d 0a - d 35a rws t rwh t 543601-27 req rqh t rqs t a t rqs t rqh figure 9. data bypass timing lh543601 256 36 2 bidirectional fifo 18
timing diagrams (contd) previous data read from fifo #2 write to fifo #1 oh t eh t es t pf a cc t cl t ch t a t t zx a t data out xz t dh t ds t pf t pf t pf t notes: 1. the port a parity error flag (pf a ) reflects the parity status of data present on the data bus. 2. the status of oe a does not gate read or write operations. 3. if oe a is left low during a write operation, then the previous data held in the output latch is written back into fifo #1. t as t ah t as t ah t as t ah t es t eh t as t ah t as t ah t as t ah a 1a a 0a oe a a 2a en a r/w a ck a d 0a - d 35a rwh t rws t rwh t rws t data in valid pf valid pf valid pf 543601-24 t rqs t rqh req a t rqs t rqh figure 10. port a fifo read/write 256 36 2 bidirectional fifo lh543601 19
timing diagrams (contd) b ck b r/w en a 0b oe b b previous data read from fifo #1 write to fifo #2 oh t eh t es t eh t es t pf b cc t cl t ch t ah t as t ah t as t a t zx t a t data out xz t data in dh t ds t valid pf valid pf valid pf pf t pf t pf t notes: 1. the port b parity error flag (pf b ) reflects the parity status of data present on the data bus. 2. the status of oe b does not gate read or write operations. 3. if oe b is left low during a write operation, then the previous data held in the output latch is written back into fifo #2. d 0b - d 35b rwh t rws t rwh t rws t 543601-25 req b rqh t rqs t rqh t rqs t figure 11. port b fifo read/write lh543601 256 36 2 bidirectional fifo 20
timing diagrams (contd) a ck a r/w en mbf a 2 mailbox in write to mailbox #1 read from mailbox #2 eh t es t dh t ds t eh t es t a t ah t as t ah t as t ah t as t ah t as t ah t as t ah t as t a 2a a 1a a 0a ck b mbf 1 oe a mbf t maximum of 2 ck cycles latency b t oh a t t zx mailbox out notes: 1. both edges of mbf 2 are synchronized to the port a clock, ck a . 2. both edges of mbf 1 are synchronized to the port b clock, ck b . 3. there is a maximum of two ck b clock cycles of synchronization latency before mbf 1 is asserted to indicate valid new mailbox data. 4. the status of mailbox flags does not prevent mailbox read or write operations. d 0a - d 35a rwh t rws t rwh t rws t mbf t 543601-22 req a t rqs t rqh t rqs t rqh figure 12. port a mailbox access 256 36 2 bidirectional fifo lh543601 21
timing diagrams (contd) mailbox in write to mailbox #2 read from mailbox #1 eh t es t dh t ds t eh t es t a t ah t as t ah t as t mbf t maximum of 2 ck a cycles latency t oh a t t zx mailbox out notes: 1. both edges of mbf 2 are synchronized to the port a clock, ck a . 2. both edges of mbf 1 are synchronized to the port b clock, ck b . 3. there is a maximum of two ck a clock cycles of synchronization latency before mbf 2 is asserted to indicate valid new mailbox data. 4. the status of mailbox flags does not prevent mailbox read or write operations. ck b r/w b en b a 0b mbf 1 ck a mbf 2 oe b d 0b - d 35b rwh t rws t rwh t rws t mbf t 543601-23 req b t rqs t rqh t rqs t rqh figure 13. port b mailbox access lh543601 256 36 2 bidirectional fifo 22
timing diagrams (contd) a ck a r/w en a 2a a 1a oe a a flag data in flag data out load flag positions read flag positions eh t es t ah t as t ah t as t ah t as t dh t ds t eh t es t ah t as t ah t as t ah t as t a 0a rf t ae 1 , ae 2 , af 1 , af 2 notes: 1. for valid flag address codes and data formats, see table 3. 2. if flag status is altered by flag programming, the updated flags will be valid within a time t rf. 3. the control register may be loaded as shown here, with a 2a , a 1a , a 0a = hll. however, it is not available for reading back. t a t a t zx t oh d 0a - d 35a rwh t rws t rwh t rws t 543601-18 req a t rqs t rqh t rqs t rqh figure 14. flag programming 256 36 2 bidirectional fifo lh543601 23
timing diagrams (contd) 543601-1 ef 2 (ef 1 ) eh t es t ef t ef t ck (ck ) ab en (en ) ab ck (ck ) b a r/w (r/w ) a b r/w (r/w ) b a req b (req a ) notes: 1. a 2a , a 1a , and a 0a all are held high for fifo access at port a. a 0b is held high for fifo access at port b. 2. parameters without parentheses apply to fifo #2 operation. parameters with parentheses apply to fifo #1 operation. 3. assertion of the empty flags is controlled by rising clock edges, whereas deassertion of the empty flags is controlled by falling clock edges. rwh t rws t rwh t rws t t rqs t rqh eh t es t en (en ) ba t rqs t rqh req a (req b ) figure 15. empty flag timing lh543601 256 36 2 bidirectional fifo 24
ae 2 (ae 1 ) eh t es t ae t ae t ck (ck ) ab en (en ) ab ck (ck ) ba eh es r/w (r/w ) a b r/w (r/w ) b a rwh t rws t rwh t rws t t t 543601-2 notes: 1. a 2a , a 1a , and a 0a all are held high for fifo access at port a. a 0b is held high for fifo access at port b. 2. parameters without parentheses apply to fifo #2 operation. parameters with parentheses apply to fifo #1 operation. 3. assertion of the almost-empty flags is controlled by rising clock edges, whereas deassertion of the almost-empty flags is controlled by falling clock edges. rqh t rqs t req (req ) ab en (en ) ba req (req ) ba rqh t rqs t figure 16. almost-empty flag timing timing diagrams (contd) 256 36 2 bidirectional fifo lh543601 25
timing diagrams (contd) ff 1 (ff 2 ) eh t es t ff t ff t ck (ck ) ab en (en ) ab ck (ck ) b r/w (r/w ) a b r/w (r/w ) b a en (en ) ba a rwh t rws t rwh t rws t 543601-3 notes: 1. a 2a , a 1a , and a 0a all are held high for fifo access at port a. a 0b is held high for fifo access at port b. 2. parameters without parentheses apply to fifo #1 operation. parameters with parentheses apply to fifo #2 operation. 3. assertion of the full flags is controlled by rising clock edges, whereas deassertion of the full flags is controlled by falling clock edges. t rqs t rqh req a (req b ) eh t es t req b (req a ) t rqs t rqh figure 17. full flag timing lh543601 256 36 2 bidirectional fifo 26
timing diagrams (contd) af 1 (af 2 ) eh t es t af t af t ck (ck ) ab en (en ) ab ck (ck ) ba r/w (r/w ) a b r/w (r/w ) b a rwh t rws t rwh t rws t 543601-4 notes: 1. a 2a , a 1a , and a 0a all are held high for fifo access at port a. a 0b is held high for fifo access at port b. 2. parameters without parentheses apply to fifo #1 operation. parameters with parentheses apply to fifo #2 operation. 3. assertion of the almost-full flags is controlled by rising clock edges, whereas deassertion of the almost-full flags is controlled by falling clock edges. t rqs t rqh req a (req b ) eh t es t en (en ) ba t rqs t rqh req b (req a ) figure 18. almost-full flag timing 256 36 2 bidirectional fifo lh543601 27
timing diagrams (contd) hf 1 (hf 2 ) eh t es t hf t hf t ck (ck ) ab en (en ) ab ck (ck ) ba eh t es t r/w (r/w ) a b r/w (r/w ) b a en (en ) ba rwh t rws t rwh t rws t 543601-5 notes: 1. a 2a , a 1a , and a 0a all are held high for fifo access at port a. a 0b is held high for fifo access at port b. 2. parameters without parentheses apply to fifo #1 operation. parameters with parentheses apply to fifo #2 operation. 3. both assertion and deassertion of the half-full flags are controlled entirely by rising clock edges, rather than by falling clock edges. t rqs t rqh req a (req b ) t rqs t rqh req b (req a ) figure 19. half-full flag timing lh543601 256 36 2 bidirectional fifo 28
a ck a r/w rt 2 ck b b r/w en a t rsh t rs t rsh t rss t es t eh t es t eh t es t rss rws t rws t notes: 1. t rss and t rsh need not be met unless a rising edge of ck a or ck b occurs while that clock is enabled. 2. t rss is the time needed to deassert rt 2 before returning to a normal fifo cycle. 3. t rsh is the time needed before asserting rt 2 after a normal fifo cycle. 4. read and write operations to fifo #2 should be disabled while rt 2 is being asserted. 543601-20 t rqs t rqh t rqs t rqh t rqs en b es t eh t es t eh t es t req a req b t rqs t rqh t rqs t rqh t rqs figure 20. fifo #2 retransmit timing diagrams (contd) 256 36 2 bidirectional fifo lh543601 29
timing diagrams (contd) b ck b r/w rt 1 ck a r/w en b t rs t rss a t rss t es t eh t es t eh t es t rsh rws t rws t notes: 1. t rss and t rsh need not be met unless a rising edge of ck a or ck b occurs while that clock is enabled. 2. t rss is the time needed to deassert rt 1 before returning to a normal fifo cycle. 3. t rsh is the time needed before asserting rt 1 after a normal fifo cycle. 4. read and write operations to fifo #1 should be disabled while rt 1 is being asserted. t rsh 543601-21 t rqs t rqh req b t rqs t rqh t rqs en a t es t eh t es t es eh t req a t rqs t rqh t rqs t rqh t rqs figure 21. fifo #1 retransmit lh543601 256 36 2 bidirectional fifo 30
timing diagrams (contd) a ck a r/w a en ef 1 b ck r/w b previous data t eh t es t eh t es t ds t dh t ds t dh t oh a t t oh a t ef t n1 n2 n1 n2 frl t ef t notes: 1. a 2a , a 1a , a 0a , and a 0b are all held high for fifo access. 2. oe a is held high. 3. oe b is held low. 4. t frl (first read latency) - the first read following an empty condition may begin no earlier than t frl after the first write to an empty fifo, to ensure that valid read data is retrieved. d 0a - d 35a d 0b - d 35b rwh t rws t rwh t rws t rwh t rws t rwh t rws t 543601-16 t rqs t rqh req a t rqs t rqh b en es t eh t t eh es t t rqs t rqh req b t rqs t rqh figure 22. fifo #1 write and read operation in near-empty region 256 36 2 bidirectional fifo lh543601 31
timing diagrams (contd) b ck b r/w b en ef 2 a ck r/w a a en t eh t es t eh t es t ds t dh t ds t dh t eh es t eh t es t ef t frl t ef t notes: 1. a 2a , a 1a , a 0a , and a 0b are all held high for fifo access. 2. oe b is held high. 3. oe a is held low. 4. t frl (first read latency) - the first read following an empty condition may begin no earlier than t frl after the first write to an empty fifo, to ensure that valid read data is retrieved. t a t a t oh t oh d 0b - d 35b d 0a - d 35a rwh t rws t rwh t rws t rwh t rws t rwh t rws t previous data n1 n2 n1 n2 543601-17 t rqs t rqh req b t rqs t rqh req a t rqs t rqh t rqh t rqs figure 23. fifo #2 write and read operation in near-empty region lh543601 256 36 2 bidirectional fifo 32
timing diagrams (contd) a ck a r/w ff 1 b ck r/w b previous data t ds t dh t ds t dh t fwl t ff t oh a t t oh a t ff t notes: 1. a 2a , a 1a , and a 0a all are held high for fifo access at port a. a 0b is held high for fifo access at port b. 2. oe a is held high. 3. oe b is held low. 4. t fwl (first write latency) - the first write following a full condition may begin no earlier than t fwl after the first read from a full fifo, to ensure that valid write data is written. d 0a - d 35a d 0b - d 35b rwh t rws t rwh t rws t rwh t rws t rwh t rws t 543601-14 a en t eh t es t eh t es t rqs t rqh req a t rqs t rqh b en es t eh t t eh es t t rqs t rqh req b t rqs t rqh figure 24. fifo #1 read and write operation in near- full region 256 36 2 bidirectional fifo lh543601 33
timing diagrams (contd) b ck b r/w ff 2 a ck r/w a a en notes: 1. a 2a , a 1a , and a 0a all are held high for fifo access at port a. a 0b is held high for fifo access at port b. 2. oe b is held high. 3. oe a is held low. 4. t fwl (first write latency) - the first write following a full condition may begin no earlier than t fwl after the first read from a full fifo, to ensure that valid write data is written. d 0b - d 35b d 0a - d 35a previous data t ds t dh t ds t dh t fwl t ff es t eh t t eh es t t oh a t t oh a t ff t rwh t rws t rwh t rws t rwh t rws t rwh t rws t 543601-15 b en t eh t es t eh t es t rqs t rqh req b t rqs t rqh t rqs t rqh req a t rqs t rqh figure 25. fifo #2 read and write operation in near -full region lh543601 256 36 2 bidirectional fifo 34
timing diagrams (contd) t es b ck b r/w b en t a word # n+1 word # n notes: 1. a 0b is held high for fifo access. 2. oe b is held low. 3. ws 0 is held high and ws 1 is held low for double-byte access. 4. data-access time t a , after the rising edge of ck b , shown for the first read cycle, applies similarly for all subsequent read cycles. d 0b - d 17b d 18b - d 35b rws t word # n+2 word # n+1 word # n word # n+2 bits 0-17 bits 18-35 bits 0-17 bits 18-35 bits 0-17 bits 18-35 bits 0-17 bits 18-35 bits 0-17 bits 18-35 543601-13 t rqs b req figure 26. port b dou ble-byte fifo #1 read access for 36-to-18 funneling 256 36 2 bidirectional fifo lh543601 35
b ck b r/w t ds t dh word # n word # n+1 word # n+2 notes: 1. a 0b is held high for fifo access. 2. oe b is held high. 3. ws 0 is held high and ws 1 is held low for double-byte access. 4. data-setup time t ds and data-hold time t dh , before and after the rising edge of ck b , shown for the first write cycle, apply similarly for all subsequent write cycles. d 0b - d 17b rws t bits 0-17 bits 18-35 bits 0-17 bits 18-35 bits 0-17 bits 18-35 543601-12 t es b en t rqs b req figure 27. port b double-byte fifo #2 write access for 18-to-36 defunneling timing diagrams (contd) lh543601 256 36 2 bidirectional fifo 36
timing diagrams (contd) t es b ck b r/w b en bits 0-8 t a word # n+1 word # n notes: 1. a 0b is held high for fifo access. 2. oe b is held low. 3. ws 0 and ws 1 both are held low for single-byte access. 4. data-access time t a , after the rising edge of ck b , shown for the first read cycle, applies similarly for all subsequent read cycles. bits 9-17 bits 18-26 bits 27-35 bits 0-8 bits 9-17 bits 18-26 bits 27-35 bits 0-8 bits 9-17 bits 18-26 bits 27-35 bits 0-8 bits 9-17 bits 18-26 bits 27-35 bits 0-8 bits 9-17 bits 18-26 bits 27-35 d 27b - d 35b d 18b - d 26b d 9b - d 17b d 0b - d 8b rws t word # n+1 word # n word # n+1 word # n word # n+1 word # n 543601-11 t rqs b req figure 28. port b single-byte fifo #1 read access for 36-to-9 funneling 256 36 2 bidirectional fifo lh543601 37
timing diagrams (contd) t es b ck b r/w b en bits 0-8 bits 9-17 bits 18-26 bits 27-35 t ds t dh word # n word # n+1 notes: 1. a 0b is held high for fifo access. 2. oe b is held high. 3. ws 0 and ws 1 both are held low for single-byte access. 4. data-setup time t ds and data-hold time t dh , before and after the rising edge of ck b , shown for the first write cycle, apply similarly for all subsequent write cycles. bits 0-8 bits 9-17 d 0b - d 8b rws t 543601-10 t rqs b req figure 29. port b single-byte fifo #2 write access for 9-to-36 defunneling lh543601 256 36 2 bidirectional fifo 38
543601-8 t rqs t ack t af t ack t ack t ack b (ck ) b (r/w ) b (req ) b (ack ) (af 2 ) a ck a r/w a req a ack af 1 rws t *** * * * indicates where a write would take place, if ack were tied to en. notes: 1. for a fifo access to occur, req and en must be held high for the required setup and hold times. 2. ack can be tied directly to en to directly gate fifo accesses. 3. req must be maintained high throughout the entire clock cycle for ack to be generated. 4. when the req/ack handshake is not used, ack can be ignored, and req may be tied high or used as a second enable. 5. parameters without parentheses apply to port a. parameters with parentheses apply to port b. starting at the third cycle after entering the 'almost-full' region, acknowledge occurs on every third cycle to prevent overrun of the full condition. outside the 'almost-full' region, acknowledge is continuous for a continuous request. 1 2 figure 30. write r equest/acknowledge handshake timing diagrams (contd) 256 36 2 bidirectional fifo lh543601 39
timing diagrams (contd) t rqs t ack t ae t ack t ack t ack b (ck ) b (r/w ) b (req ) b (ack ) (ae 1 ) a ck a r/w a req a ack ae 2 rws t starting at the third cycle after entering the 'almost-empty' region, acknowledge occurs on every third cycle to prevent underrun of the empty condition. outside the 'almost-empty' region, acknowledge is continuous for a continuous request. * indicates where a read would take place, if ack were tied to en. notes: 1. for a fifo access to occur, req and en must be held high for the required setup and hold times. 2. ack can be tied directly to en to directly gate fifo accesses. 3. req must be maintained high throughout the entire clock cycle for ack to be generated. 4. when the req/ack handshake is not used, ack can be ignored, and req may be tied high or used as a second enable. 5. parameters without parentheses apply to port a. parameters with parentheses apply to port b. * * ** * 543601-9 1 2 figure 31. read request/acknowl edge handshake lh543601 256 36 2 bidirectional fifo 40
package diagrams 132 pqfp dimensions in mm [inches] maximum limit minimum limit 132pqfp (pqfp132-p-s950) 28.02 [1.103] 27.86 [1.097] 0.635 [0.025] typ non-accum 4.57 [0.180] 4.06 [0.160] 0.51 [0.020] min. 24.21 [0.953] 24.05 [0.947] 28.02 [1.103] 27.86 [1.097] 27.69 [1.090] 27.18 [1.070] 27.69 [1.090] 27.18 [1.070] section 0.10 [0.004] 0.25 [0.010] typ. 0.51 [0.020] min. 0.15 [0.006] 0 - 8 45 chamfer top view 24.21 [0.953] 24.05 [0.947] 132-pin pqfp 256 36 2 bidirectional fifo lh543601 41
dimensions in mm [inches] maximum limit minimum limit 144tqfp (tqfp-144-p-2020) 0.50 [0.020] typ. 0.20 [0.008] 0.09 [0.004] 20.0 [0.787] basic 144tqfp 1.45 [0.057] 1.35 [0.053] detail 20.0 [0.787] basic 1.60 [0.063] ref. max 0.15 [0.006] 0.05 [0.002] 22.0 [0.866] basic 0.27 [0.010] 0.17 [0.007] 22.0 [0.866] basic 0.75 [0.030] 0.47 [0.019] 1.00 [0.039] ref. 144-pin tqfp lh543601 256 36 2 bidirectional fifo 42
ordering information 20 25 30 35 cycle times (ns) m 144-pin, thin quad flat package (tqfp144-p-2020) p 132-pin, plastic quad flat package (pqfp132-p-s950) lh543601 device type x package - ## speed 256 x 36 x 2 bidirectional fifo example: lh543601p-20 (256 x 36 x 2 bidirectional fifo, 20 ns, 132-lead, plastic quad flat package) 543601-37 256 36 2 bidirectional fifo lh543601 43

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